The present invention relates to a data processing system and an image processing system in the field of an information terminal such as a personal computer or a workstation for processing the image data allocated on a memory and, more particularly, to a technique which is effective when applied to a high-speed image processing system for accessing a memory at a high speed in synchronism with a clock.
In the image processing system, a drawing display processor executes a drawing processing upon a frame buffer in accordance with drawing commands or parameters transferred from a CPU. This drawing display processor may execute the drawing processing in accordance with the drawing commands or parameters which are arranged in advance in the frame buffer or a special purpose local memory. Moreover, the drawing display processor reads out the necessary display data from the frame buffer in accordance with the horizontal and vertical synchronizing timings and the dot rate of the monitor and displays them on the monitor through a dot shifter. The clock generator produces a fundamental clock and a dot clock on the basis of the reference frequency of a quartz oscillator and feeds them to the drawing display processor and the dot shifter. As the frame buffer of such image processing system, there can be adopted a DRAM (i.e., Dynamic Random Access Memory) or a multi-port DRAM which is given such a large storage capacity as is required for the bit map arrangement of the display data.
In the image processing system used in a facsimile, a printer or a graphic device of the prior art, on the other hand, there are used a high-speed SRAM (i.e., Static Random Access Memory) as a local processing referring to peripheral pixels, as disclosed in Japanese Patent Laid-Open No. 261969/1986, and a DRAM as a large-capacity memory for storing code data and font data.
In the trends of the field of the information terminal device of recent years such as a personal computer or workstation for business uses, the high quality, operation speed and capacity are advanced to increase the data bus width in case the frame buffer is constructed of a standard DRAM. In other constructions adopted, the drawing processing efficiency is improved by constructing the frame buffer of the multiport DRAM. In accordance with this, there arises a problem that the cost for the system arises.
On the other hand, the synchronous DRAM has been noted as a large-capacity memory. This synchronous DRAM can input/output data, addresses and control signals in synchronism with clocks, as different from the DRAM of the prior art, so that it can realize a large-capacity memory equivalent to the DRAM at a speed as high as that of the SRAM. Thus, the synchronous DRAM can achieve a higher speed access and a larger capacity more than those of the DRAM of the prior art at a reasonable cost. This synchronous DRAM can designate how many data are to be accessed for one selected word line, in terms of a bust length , for example. In case the burst length is N, an N number of data can be sequentially read or written by switching the selected states of a column line by an internal column address counter. Incidentally, the application of the synchronous DRAM to a main memory or for graphics is disclosed, for example, in the electronic technology on pp. 24 to 28 (1993) of xe2x80x9cApplications to Main Memory or Graphics of High-Speed DRAMxe2x80x9d.
We have examined an image processing system which is enabled to access a large-capacity a high-speed memory at a low cost by integrating a high-speed processing memory and a large-capacity memory Specifically, we have examined the case in which a system is to be constructed by using the synchronous DRAM as a memory having a function to latch addresses, data and control signals in synchronism with clocks, and have come to the conclusions discussed below.
Firstly, in order to realize a high-speed access while holding the reliability of an accessing operation, the skews between the data, addresses and control signals outputted by the circuit modules and the clock signals are required to have a small value by the characteristics of the synchronous DRAM for inputting/outputting the data, addresses and control signals in synchronism with the clocks.
Secondly, when drawing a straight line in an arbitrary direction, the memory addresses are not continuous in the same row address so that the burst length is desired to have a value 1. In a rectangular smearing drawing for clearing the memory, on the other hand, the memory addresses are continuous in the same row address so that the burst length is desired to have a value N (N greater than 1). Thus, the processing of changing the burst length in accordance with the drawing processing content is desired to be executed in the display control system.
Thirdly, there is further examined the case in which the synchronous DRAM is used to construct the system. Thanks to the use of the synchronous DRAM, a clock timing for outputting the read data, for example, can be designated after an address to be accessed has been issued, so that a next address can be issued before the read processing has been completed. In case the addresses are to be subsequently issued, they are limited to belong to the same row address. In order to access the different row addresses in the same bank, therefore, there is required a mishit processing such as a precharge processing.
An object of the present invention is to provide a technique for solving the several problems, which are caused when a clock-synchronized type memory having a high-speed operation and a large capacity such as the synchronous DRAM is to be applied to an image processing system, and for realizing an inexpensive, high-performance image processing system and a data processing system, and a data processor for the systems.
More specifically, an object of the present invention is achieved such processing for changing the burst length according to a processing content which occurs when a system having an integrated memory is to be constructed by using the synchronous DRAM. Another object is to improve the bus throughout of the memory at a low cost in accordance with the burst length. A further object is to realize the mishit processing at a low cost and at a high speed. A further object is to provide a data processor optimized for controlling the access of a clock-synchronized type memory such as the synchronous DRAM having a high-speed operation and a large capacity.
The foregoing and other objects and novel features of the present invention will become apparent from the following description to be made with reference to the accompanying drawings.
Representatives of the invention to be disclosed herein will be briefly described in the following. Specifically, the present invention is coarsely divided into the feed of clock signals to a memory such as the synchronous DRAM, the setting of a mode register for designating the operation modes, and the processing of a mishit.
 less than  less than Feed of Clocks greater than  greater than 
A data processor comprises : bus control means (14) interfaced with a memory (22) such as a synchronous DRAM for inputting addresses, inputting/outputting data and inputting control signals in synchronism with a clock signal (CLK) fed from the outside; a plurality of data processing modules (12, 13) coupled to said bus control means for individually producing data and addresses to access said memory; and clock feed means for feeding said data processing modules with individually intrinsic operation clock signals and for feeding the clock signals for accessing said memory to the outside in synchronism with the operations of said data processing modules actuated by an intrinsic operation clock fed.
In order that the data processor may be easily applied to the case in which the plurality of data processing modules have different operation speeds, said clock feed means includes: a plurality of clock drivers (16c, 16s) disposed for the individual operation speeds of said plurality of data processing modules; and a clock selector (25) for selecting that of the outputs of said clock drivers, which corresponds to the data processing module acting as an access subject, to feed the selected output to the outside.
In order to avoid the competition of the clock signal in case said plurality of data processors share said memory, said data processor further comprises a clock buffer (160) adapted to output the clock signal from said clock feed means to the outside and made selectively controllable to a high output impedance stage.
In order to commonly connect a ROM (i.e., a Read Only Memory) stored with parameters for the data processing and to use it, said bus control means includes means for deciding it from an address outputted, when a second memory having a lower access speed than that of said memory coupled thereto is to be accessed, that the access is to said second memory, thereby to make the memory cycle of the access to said second memory longer than that to said memory.
Said bus control means includes means (143, 144 and 1495c) for outputting, as control signals, commands to determine the operation modes of said memory in response to an instruction of an access to said memory from said data processing modules.
Said bus control means, said data processing module and said clock feed means are formed over one semiconductor substrate. Moreover, said data processor further comprises: a memory adapted to receive an address input, data input/output and a control signal in synchronism with said clock signal and coupled to said bus control means; and clock generating means coupled to said clock feed means.
 less than  less than Mode Register Setting greater than  greater than 
A data processing system comprises: a rewritable memory adapted to receive an address input, data input/output and a control signal in synchronism with a clock signal and to update the address, which is preset in an internal address counter (207), at times in number corresponding to the set number of a mode register (30), to read/write the data sequentially; and a data processor (11) for generating data and addresses to access said memory and for utilizing said memory in at least a frame buffer to process image data, wherein said data processor includes means for issuing a command and a register set value to set said mode register in accordance with the condition at the data processing time.
Said data processing system further comprises an input terminal for receiving an external signal (135) to regulate the timing for issuing a command to set said mode register. Moreover, said data processor further includes instruction control means (51 to 57) for executing the instruction which is allocated to the issue of the command for setting said mode register. Still moreover, said data processor further includes: an address decoder (1481) for detecting an internal access to the address which is allocated to the issue of the command for setting said mode register; and a sequencer (143) for issuing said mode register setting command in accordance with the result of detection by said address decoder and for outputting the data to be subjected to said internal access, as the set value for a command register to the outside.
A data processing system for improving the throughput of a data processing accompanied by a memory access comprises: a memory (22); and a data processor (11) for accessing said memory to processing image data, wherein said memory includes a plurality of memory banks (200A, 200B) and is enabled to receive an address input, data input/output and a control signal in synchronism with a clock signal (CLK), wherein said memory has a burst mode, in which it is accessed while updating an address preset in an internal address counter (207), so that it can receive an address active command for setting the access address in another memory bank in parallel with the operation of a memory bank being operated in the burst mode, and wherein said data processor includes: data processing modules (12, 13) for producing data and addresses to access said memory and for processing the image data by using said memory in at least a frame buffer; arid bus control means (14) for issuing said active address command in response to the instruction of an access from said data processing module for a memory bank different from the memory bank being accessed in the burst mode, to enable the access address to be set in advance.
 less than  less than Mishit Processing 1 greater than  greater than 
A data processing system for preventing the disturbance of the pipeline which is realized by reading/writing a plurality of memories in parallel comprises first and second memories (82a, 82b) for latching row addresses to enable the same row address as one once latched to be sequentially accessed by updating a column address, and for receiving an address input, data input/output and a control signal in synchronism with a clock signal; first and second memory buses (821a, 822a, 821b, 822b) allocated to said first and second memories, respectively; first and second bus control means (74a, 74b) allocated to said first and second memory buses, respectively; a data processing module (71) coupled to said first and second bus control means for producing data and addresses to access said first and second memories thereby to process the data read out from said first memory and for producing and outputting the access addresses to said first and second memories in parallel to store the result of the data processing in said second memory; delay means (731, 732) for transmitting the access address for said second memory, which is outputted from said data processing module, to said second memory with a delay time period corresponding to the time period for said data processing; first mishit detecting means (72b) for detecting whether or not the row address outputted from said data processing module toward said first memory is coincident to the preceding row address fed; second mishit detecting means (72a) for detecting whether or not the row address outputted from said data processing module toward said second memory is coincident to the preceding row address fed, such that its detection timing is made substantially concurrent with that by said first mishit detecting means; and means (76) for interrupting the operation of said data processing module while the row address relating to said mishit is being updated, when either said first or second mishit detecting means detects the incoincidence.
A data processing system for improving the reliability of a processing at the time of a mishit accompanying a change in a memory access subject comprises: a memory (182a) for latching a row address to enable the same address as the once latched one to be sequentially accessed by updating a column address and for receiving an address input, data input/output and a control signal in synchronism with a clock signal; a plurality of data processing modules (71, 75) for producing data and addresses to access said memory; mishit detecting means (72a) for detecting whether or not the row address outputted from said data processing modules toward said memory is coincident to the preceding row address fed; detect means (725) for detecting a change in the data processing modules to access said memory; and bus control means (74a) for instructing said memory to update the row address for said access in response to either the detection of the incoincidence by said mishit detecting means or the detection of the change in the access subject by said detect means.
 less than  less than Mishit Processing 2 greater than  greater than 
A data processing system for processing data in a pipeline manner while reading/writing a plurality of memories in parallel comprises: first and second memories (82a, 82b) for latching a row address to enable the same row address as the once latched one to be sequentially accessed by updating a column address, and for receiving an address input, data input/output and a control signal in synchronism with a clock signal; memory buses (821a, 822a, 821b, 822b) allocated to said first and second memories, respectively; bus control means (74a, 74b) allocated to said memory buses, respectively; a data processing module (71) coupled to said individual bus control means for producing data and addresses to access said first first and second memories thereby to process the data read out from said first memory, and for producing the access addresses in parallel for said first and second memories to store the results of the data processing in said second memory; and delay means (731, 732) for transmitting the address address for said second memory, which is outputted from said data processing module, to said second memory with a delay time period corresponding to that for said data processing. In short, the first and second memories are caused to transfer the information in parallel through the individual memory buses, so that the access addresses for the two memories are outputted in parallel by the data processing module, and the timing for the two access addresses outputted in parallel to be inputted to the corresponding memories is uniquely determined by the delay means.
In order to prevent the disturbance of the pipeline data processing, the data processing system further comprises: mishit means for detecting at substantially the same timing whether or not the row addresses of the individual access addresses outputted in parallel from said data processing module to said first and second memories are coincident to the preceding row address fed; and means for interrupting the operation of said data processing module, while the row address of said mishit is being updated, when the incoincidence of said row address is detected by said mishit detecting means. More specifically, a data processing system for preventing the disturbance of the pipeline realized by reading/writing a plurality of memories in parallel comprises: first and second memories (82a, 82b) for latching row addresses to enable the same row address as one once latched to be sequentially accessed by updating a column address, and for receiving an address input, data input/output and a control signal in synchronism with a clock signal; first and second memory buses (821a, 822a, 821b, 822b) allocated to said first and second memories, respectively; first and second bus control means (74a, 74b) allocated to said first and second memory buses, respectively; a data processing module (71) coupled to said first and second bus control means for producing data and addresses to access said first and second memories thereby to process the data read out from said first memory and for producing and outputting the access addresses to said first and second memories in parallel to store the result of the data processing in said second memory; delay means (731, 732) for transmitting the access address for said second memory, which is outputted from said data processing module, to said second memory with a delay time period corresponding to the time period for said data processing first mishit detecting means (72b) for detecting whether or not the row address outputted from said data processing module toward said first memory is coincident to the preceding row address fed; second mishit detecting means (72a) for detecting whether or not the row address outputted from said data processing module toward said second memory is coincident to the preceding row address fed, such that its detection timing is made substantially concurrent with that by said first mishit detecting means; and means (76) for interrupting the operation of said data processing module while the row address relating to said mishit is being updated, when either said first or second mishit detecting means detects the incoincidence.
According to the above-specified means, the aforementioned memory such as a synchronous DRAM has to input/output data, addresses and control signals in synchronism with a clock and accordingly has to be fed with the same clock, multiplied clock or divided clock as that of a data processor to access the synchronous DRAM. In case, however, the output of a clock generator is fed in parallel to the data processor and the synchronous DRAM, the margin of the data and addresses for the clock and the setup and hold time of the control signals cannot be afforded due to the skew of the clock and the internal delay of the processor. In order to solve this problem, a synchronizing clock signal is fed from the data processor to the synchronous DRAM. As a result, the clock to be fed to the synchronous DRAM can match the delay of the data, addresses and control signals to allow a design with a margin.
In case the data processing module operating at different frequencies is present in the aforementioned data processor, there is adopted a construction in which the clock of the data processing module acting as a bus master is selected in the data processor and fed to the synchronous DRAM. As a result, the clock to be fed to the synchronous DRAM and the delay in the data, addresses and control signals can be adjusted to each other at the unit of the data processing module acting as the bus master thereby to allow a design with a margin.
In a method for opening the synchronous DRAM to the external system, the data, addresses and control signals to the synchronous DRAM of the data processor and the clock terminals are controlled to a high impedance. As a result, the design can be made with a margin in case the external system makes a direct access to the synchronous DRAM.
The mode register included in the synchronous DRAM is a register for designating the operation mode of the synchronous DRAM. An optimum setting of the mode register can be made by adopting the method of setting the mode register according to the internal architecture and the processing content of the processor. In the straight line drawing of an arbitrary direction, for example, the memory addresses are not continuous in the same row address so that the burst length to be set in the mode register is desired to have a value 1. In a rectangular smearing drawing for clearing the memory, on the other hand, the memory addresses are continuous in the same row address so that the burst length is desired to have a value N (N greater than 1). Thus, the processing of changing the burst length in accordance with the drawing processing content is required. In the present invention, therefore, the mode register is dynamically changed according to the various processing contents. The bus throughput of the memory can be improved at a low cost in conformity to the burst length.
The condition for a high-speed transfer is restricted within the common row address, and it is necessary to issue a precharge command and a row address activation command in case the transfer extends to a different row address. In the present invention, therefore, the physical memory addresses and the logical coordinates are mapped such that the adjoining addresses in the same row address in the X direction, for example, never fail to be arranged at different bank addresses. In case the burst length is set to N (N greater than 1), the precharge command and the active command can be generated, while the data are being accessed to the synchronous DRAM at present, for a bank different from that being accessed, so that the bus throughput can be improved. The drawing processing module, the display processing module or the bus control unit is equipped therein with means for arithmetically operating the address and means for deciding the switching of the row address. When the change in the row address is detected, the sequencer in the bus control unit issues the precharge command and the row address activation command and then a column address. Thus, the read/write operations are speeded up.
When the result of image processing with quick reference to the address range of the synchronous DRAM used as the line memory is to be written in the address range of the synchronous DRAM used as the page buffer, the pipeline in the image processing unit collapses to interrupt the processing if a mishit occurs independently in the read/write operations. If the mishit occurs in both the reading operation and the writing operation, the memory read/write in the pipeline are synchronized by handling the concurrent occurrence of mishits. Thus, there is adopted write address mishit detecting means for detecting the mishit at the write side at substantially the same timing as that of the mishit at the read side.
Since the mishit is thus forcibly caused at the time of changing the access subjects for the memory, the indefiniteness of the mishit decision at the time of reopening the operation of the data processing module which has its operation interrupted as the memory access subjects are changed can be eliminated to improve the reliability of the processing at the time of a mishit.